1. Field of the Invention
The present invention generally relates to memory devices, and more particularly to a memory device which is suitably applied for a frame buffer memory of an image display apparatus, for example.
2. Prior Art
The conventional image display apparatus comprises a frame buffer memory, a display controller and a display apparatus which employs a raster scan system. Image data including figure data, character data and the like are stored in the buffer memory based on commands from a CPU (a Central Processing Unit). The display controller successively reads out the image data from the buffer memory and outputs the image data to the display apparatus wherein an image according to the image data will be displayed on a screen thereof.
In the above image display apparatus, it is necessary to perform two kinds of accesses such as an access from the CPU and an access from the display controller. In this case, it is possible to employ a method in which the access from the CPU is permitted only in a blanking period of a horizontal scanning or a vertical scanning. In addition, it is possible to employ another method in which a memory access timing is divided into several time slots and specific time slots are assigned to the display controller and remaining time slots other than the specific time slots are assigned to the CPU.
However, the access from the CPU is considerably limited in both of above methods. Hence, the dual port memory is widely used and applied for performing the access from the CPU and the access from the display controller in parallel. This dual port memory has a random port and a serial port therein. And, it is possible to write in and read out data as a general RAM (Random Access Memory) via the random port, and it is also possible to input and output serial-data. Hereinafter, a series of data each of which are constituted by predetermined bits will be referred to as the serial-data, and an operation for inputting and outputting the serial-data based on serial-access will be referred to as "a serial I/O operation" in the present specification. Hence, the access from the CPU is performed by use of the random port, and the access from the display controller is performed by use of the serial port. This technique has been already disclosed in a magazine named "Nikkei Electronics" of May 20th. in 1985, no. 369, pp. 195 to pp. 219, for example.
FIG. 6 is a block diagram showing an example of the conventional dual port memory. In FIG. 6, 1 to 4 designate memory cell arrays each of which is constructed by memory cells of 256 rows and 256 columns. In the memory cell arrays 1 to 4, it is possible to perform an access in two kinds of modes including a random-access mode and a serial-access mode.
In the usual random-access mode, row addresses and column addresses are successively supplied from an address buffer 5 and are respectively decoded in a row decoder 6 and column decoders 11 to 14 so as to obtain addresses of the memory cell arrays 1 to 4. The four data of four bits are respectively read from the same addresses of the memory cell arrays 1 to 4. This four data of four bits are respectively passed through I/O gates of sense amplifiers 15 to 18 and are transferred to I/O buffers 21 to 24 wherein the four data of four bits are outputted to external devices as four output data IO0 to IO3.
On the other hand, write-in data IO0 to IO3 for the memory cell arrays 1 to 4 are read from the I/O buffers 21 to 24 and are supplied to the I/O gates of sense amplifiers 15 to 18 by an unit of four bits. The write-in data IO0 to IO3 are respectively written into the same addresses of the memory cell arrays 1 to 4. Thus, it becomes possible to simultaneously write the four data of four bits into the same arbitrary addresses of the four memory cell arrays 1 to 4 and simultaneously read the four data therefrom. As the usual RAM, this dual port memory can read and write the data at random.
Next, description will be given with respect to the serial-access mode. The memory cell arrays 1 to 4 are respectively connected to data registers 31 to 34 each of which has a word length of 256 bits. Hence, it is possible to transfer the data of one row to the memory cell arrays 1 to 4 at one time. More specifically, four data written into the memory cell arrays 1 to 4 are respectively transferred to the data registers 31 to 34 by one row (in a read-data transferring operation), and four serial-data inputted to the data registers 31 to 34 are respectively transferred and written into the memory cell arrays 1 to 4 by one row (in a write-data transferring operation).
In addition, pointers 35 to 38 are respectively attached to the data registers 31 to 34 for determining which bit within 256 bits is inputted and outputted (as a bit address). These pointers 35 to 38 are respectively constituted as shift registers of 256 bits wherein a column address supplied from the address buffer 5 is set as an initial value (or an initial bit). This initial bit is shifted by one bit based on a serial control clock SC and is outputted as the bit address for the data registers 31 to 34.
In case of a serial output operation, four read-data transferred to the data registers 31 to 34 are respectively and successively transferred to serial I/O buffers 41 to 44 wherein the four read-data are started to be stored therein from the bit address. And, the serial I/O buffers 41 to 44 output the four read-data as serial output data SD0 to SD3. On the other hand, in case of a serial input operation, the serial data SD0 to SD3 are respectively passed through the serial I/O buffers 41 to 44 and are successively inputted in series to the data registers 31 to 34 wherein the serial-data SD0 to SD3 are inputted in the bit addresses thereof assigned by the pointers 35 to 38. After the serial inputting operation is completed, the data registers 31 to 34 transfer all of the write-data into the memory cell arrays 1 to 4 at one time. Thus, it becomes possible to perform serial I/O operation from an arbitrary bit address of the row data.
In FIG. 6, 45 designates a clock generator started by a row address strobe signal RAS or a column address strobe signal CAS, 46 designates a refresh address counter for outputting a refresh address, 47 designates a write clock generator for outputting a clock in a data writing cycle, and 48 designates a transfer controller for controlling a data transfer performed between the memory cell arrays 1 to 4 and the data registers 31 to 34.
FIG. 7 is a timing chart showing an operation of the conventional dual port memory. When an usual random-access operation is performed, a value of an output enable signal 0E becomes "0" (hereinafter, an expression such as "a value of a signal becomes "0" or "1"" will be simply referred to as another expression such as "a signal becomes "0" or "1"" in the present specification) at a rising time of a row address strobe signal RAS so as to assign that the random-access operation will be started (as shown in FIG. 7(f)). At the same time, the row addresses of the memory cell arrays 1 to 4 are assigned (as shown in FIG. 7(c)). In addition, the column addresses are assigned at a time when the column address strobe signal CAS rises. Thus, it is permitted to transfer data between the memory cell arrays 1 to 4 and the data registers 31 to 34, however, usual read-out and write-in operations can be performed. In other words, the row addresses are set in the row decoder 6 and the column addresses are respectively set in the column decoders 11 to 14 by the signals RAS and CAS. Hence, the data IO0 to IO3 of four bits are executed to be read from and written into the memory cell arrays 1 to 4 wherein the data IO0 to IO3 are read from and written into the addresses thereof assigned by the above row addresses and column addresses (as shown in FIG. 7(e)).
Next, the output enable signal OE becomes "1" (which indicates that the data are transferred) and a write enable signal WE becomes "0" (which indicates "a reading condition") at a rising time of the signal RAS. At the same time, it is assigned to transfer the read-data, and the row addresses are assigned so that the present operating cycle is put into a data transfer cycle. Then, the output enable signal OE is falling down so that the memory cell arrays 1 to 4 transfer all of the row data assigned by the row addresses to the data registers 31 to 34 at one time as read-data. In this case, the column addresses are used for initializing serial output start addresses to the pointers 35 to 38.
As shown in FIG. 7(g) to FIG. 7(i), serial data transferred into the data registers 31 to 34 are outputted while a serial enable signal SE is kept "1". In other words, the bit addresses of the pointers 35 to 38 are respectively renewed by one based on the serial control clock SC. The data registers 31 to 34 respectively output the data thereof assigned by the bit addresses via the serial I/O buffers 41 to 44 as serial-data SD0 to SD3 of four bits. On the other hand, serial-data inputted into the data registers 31 to 34 are written into the memory cell arrays 1 to 4 by a transfer of write-data.
In above conventional dual port memory, however, following disadvantages (1) to (3) are occurred. (1) In the case where the serial-data are to be outputted continuously as shown in FIGS. 7(f) and 7(g), the output enable signal OE must be synchronized with the serial control clock SC. For example, both of times t.sub.SDD and t.sub.SDH are set to times more than 10 ns. Thus, a timing synchronization is required and it is difficult to design the dual port memory.
(2) It is impossible to reload partial row data of the memory cell arrays 1 to 4 with serial-data. In order to perform this reloading operation, above row data are firstly transferred to the data registers 31 to 34 as read-data, and the serial-data are inputted into the data registers 31 to 34 so as to only exchange the data in reloading portion of the arrays 1 to 4. The data registers 31 to 34 transfer the serial-data to the original rows of the memory cell arrays 1 to 4 as write-data. However, it is only permitted to output the serial-data and it is impossible to input the serial-data after the memory cell arrays 1 to 4 transfer read-data to the data registers 31 to 34 in the conventional dual port memory. Hence, the conventional dual port memory suffers a problem in that the partial row data can not be reloaded.
(3) It is impossible to input serial-data sequentially. In other words, the serial-data must be stopped to be inputted while all of the serial write-data stored in the data registers 31 to 34 are transferred to the memory cell arrays 1 to 4 at one time. Hence, the conventional dual port memory suffers a problem in that the serial-data can not be sequentially inputted thereto.